The microelectronic industry is continually striving to produce ever faster and smaller microelectronic devices for use in various mobile electronic products, such as portable computers, electronic tablets, cellular phones, digital cameras, and the like. As these goals are achieved, the fabrication of the microelectronic devices becomes more challenging. One such challenging area relates to the interconnect layers that are used to connect the individual devices on a microelectronic chip and/or to send and/or receive signals external to the individual device(s). Interconnect layers generally comprise a dielectric material having conductive interconnects (lines), such as copper and copper alloy, coupled to the individual devices. The interconnects (lines) generally comprise a metal line portion and a metal via portion, wherein the metal line portion is formed in a trench within the dielectric material and the metal via portion is formed within a via opening that extends from the trench through the dielectric material. It is understood that a plurality of interconnection layers (e.g., five or six levels) may be formed to effectuate the desired electrical connections.
As these interconnects are manufactured at smaller pitches (e.g. narrower and/or closer together), it becomes more and more difficult to properly align the trenches and the vias within and between the desired interconnect layer. In particular, during manufacturing, the location of the via edges with respect to the interconnect layer or line it is to contact will have variation (e.g. be misaligned) due to natural manufacturing variation. A via, however, must allow for connection of one interconnect layer to the desired underlying interconnect layer or line without erroneously connecting to a different interconnect layer or line. If the via is misaligned and contacts the wrong metal feature (e.g. misses line below and/or connects two lines), the microelectronic chip may short circuit resulting in degraded electrical performance. One solution to address this issue is to reduce the trench and the via size (e.g. making the via narrower). However, reducing the trench and the via size means that the aspect ratio of the openings of the trench and the via may be high. As will be understood to those skilled in the art, high aspect ratio may result in a potential reduced yield due to voiding during the deposition of conductive material (metallization) used to form the interconnects.